Low Cost Techniques for High-Speed Implementation of Decision Feedback Equalizers for FPGAs

In modern digital communications throughput rates in the order of gigabits per second are not uncommon. Hence there is a need for fast equalizing filters. While all feed forward filters can easily be pipelined, therefore sped up, the feedback filter (FBF) of decision feedback equalizers is the bottleneck of its performance. A simple, extremely...

Reordering DRAM Requests for Improved Bandwidth Utilization

The performance gap between processors and memory has grown larger and larger in the last years. With the emergence of the multicores this problem is additionally accelerated. Stalling row changes in the DRAM increase this gap even more, because the maximum theoretical bandwidth cannot be reached. The solution that is proposed in this thesis is...

Architecture-Level Fault-Tolerance Techniques for Biomedical Implants

In this thesis the design and implementation of a new fault-tolerant architecture is described. The design targets both soft and hard faults by implementing a combination of known fault-tolerance tech niques in an efficient way. The proposed architecture allows a trade-off to be made between performance and fault tolerance by means of...

SIMD Floating Point Extension for Ray Tracing

In the last decade, the importance of graphics capabilities have become very important in the mobile market. As a result low power embedded solutions for mobile devices have been eveloped to run computationally intensive graphics applications, which extensively uses floating point calculations. The work proposed in this thesis target the...

System Level Support for Dynamic Partial Reconfiguration

In this thesis a generic approach for integrating a dynamically reconfigurable device into a general purpose system interconnected with a high-speed interconnect, is described. The system dynamically installs and executes hardware instances implementing functions to accelerate parts of a particular workload. The hardware descriptions of the...

Multi-input Embedded Real-time Software Defined Radio

This master thesis work is inspired by the practical aspects of the Analytical Constant Modulus Algorithm (ACMA) proposed by Alle-Jan van der Veen and Arogyaswami Paulraj. The ACMA deals with the beamforming problem associated with constant modulus co-channel signal interference in wireless communication. Co-channel interference occur when...

Fault-Tolerant Platform for Intra-Spacecraft Modular Wireless Sensor Network

Wireless sensor networks are becoming ubiquitous in terrestrial applications. In this thesis we present a platform for wireless on-board spacecraft sensor networks with focus on the sensors that bring high 'added value' to existing space systems while becoming wireless. A novel multi-gateway architecture that uses dual hardware redundancy is...

A Co-processor for a Secure Implantable Medical Device

This work describes an energy efficient solution for secure communication between an Implantable Medical Device (IMD) and a user. For the security part a communication protocol has been selected which supports entity-authentication, message-authentication and confidentiality. For achieving low power and energy consumption the following setup has...

Modular RT-Motion USB

During the course of this thesis, RTM-USB (Real Time Motion on Universal Serial Bus) has grown from a single board motor controller to a motion control platform. The original RTM-USB board, containing a CPU and two motor drivers, has been extended (hardware wise) with a network/bus interface which makes it easy to expand the hardware...

Exploring suitable Adder Designs for Biomedical Implants: A gracefully-degradable, fault-tolerant, and highly resource-constrained adder for SiMS

Modern applications demand extremely low power budgets in computer architectures for battery-operated devices. In the particular case of implantable devices —the main focus of this thesis— the system must have a long life span and batteries may not be possible or easy to recharge. In addition to power, chip area is also of major concern in this...

Fine-Grain Runtime Fault Diagnosis for Reconfigurable Logic Blocks

The ever-shrinking technology features have as a direct consequence the increase of defect density in VLSI chips. Going into the nano-scale era, the fabrication procedures cannot keep improving at the pace of the aforementioned shrinking of technology features. Fault Tolerance emerges as a much cheaper solution and it is imperative in the future...

Analysis and Implementation of the H.264 CABAC entropy decoding engine

In this thesis we present an FPGA software/hardware co-design for the CABAC decoder. CABAC is the Context-based Adaptive Binary Arithmetic Coding used in the H.264/AVC video standard. This standard gives better compression effciency, but with greater complexity and implementation cost. A large part of this cost comes from the CABAC entropy...

Performance analysis of SCISM organization applied to the IA-32 architecture

There is a huge variety of processor microarchitectural techniques to decrease the program execution time, such as pipelining, branch prediction, and different methods to exploit the Instruction Level Parallelism (ILP). The Superscalar and VLIW machines are designed to exploit the ILP available in applications. These architectures improve...

Scalability of Bioinformatics Applications for Multicore Architectures

Exponential growth in biological sequence data combined with the computationally intensive nature of bioinformatics applications results in a continuously rising demand for processing power. Microprocessor complexity and, more importantly, computational capability increases as well, through transistor budgets that grow in line with Moore's law....

Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms

This thesis presents a feasibility analysis for hardware acceleration of the pattern recognition algorithms used by the Media Knowledge Engineering department at the Delft University of Technology. The feasibility analysis is conducted on a number of different algorithm classes. The Parzen Window algorithm appeared to be the most suitable option...

Efficient pre-filtering techniques for packet inspection

Network Security is a significant issue nowadays. The information flow is enormous and the attacks have been substantially evolved.Every single packet of the flow must be scanned in deep and checked with all known attack rules (Deep Packet Inspection) to determine whether it is malicious. However, the task of Deep Packet Inspection requires a...

3D Transesophageal echocardiography using a fast-rotating transducer

Echocardiography is a diagnostic modality which is widely used in cardiology, using ultrasound to image the living heart and assess its physiological function. Three-dimensional echocardiography surpasses the visual limitations of conventional echocar-diography, offering a three-dimensional perspective of the heart. Traditional techniques for...