Design of a Duty-Cycled Fractional-N ADPLL Based on Instantaneous Start-up LC DCO and High-precision DTCs

This thesis deals with the design of a duty-cycled, fractional-N and low-noise Phase Locked Loop (PLL) used for Ultra-Wideband applications in 40 nm process. This is the first-ever Duty-Cycled PLL (DCPLL) that is designed with an LC oscillator and brings down the noise record for DCPLLs by more than 1 order of magnitude. Due to the special...