A 1-GS/s 6–8-b Cryo-CMOS SAR ADC for Quantum Computing

This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6-8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry readout for quantum computing. To optimize the...

A Cryo-CMOS PLL for Quantum Computing Applications

This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated...

A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing

This paper presents a floating inverter amplifier (FIA) that performs high-linearity amplification and sampling while driving a 2<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> time-interleaved (TI) SAR ADC, operating from room temperature (RT) down to 4.2 K. The power-efficient FIA...

A Cryo-CMOS Digital Cell Library for Quantum Computing Applications

We present a digital cell library optimized for 4.2 K to create controllers that keep quantum processors coherent and entangled. The library, implemented on a standard 40-nm CMOS technology, was employed in the creation of the first 4.2 K RISC-V processor. It has achieved a minimum supply voltage of 590 mV, energy-delay product of 37 fJ/MHz,...

Cryo-CMOS Circuits and Systems for Quantum Computing Applications

A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum...

Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures

Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-μm and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact...