AEx

AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors

Hirvonen, Alex (Tampere University)
Leppänen, Topi (Tampere University)
Hepola, Kari (Tampere University)
Multanen, Joonas (Tampere University)
Hoozemans, J.J. (TU Delft Computer Engineering)
Jääskeläinen, Pekka (Tampere University)

2023

Modern High Level Synthesis (HLS) tools succeed well in their engineering productivity goal, but still require toolset and target technology specific modifications to the source code to guide the process towards an efficient implementation. Furthermore, their end result is a fixed function accelerator with limited field and runtime flexibility. In this paper we describe the status of AEx, a novel work-in-progress HLS tool developed in the FitOptiVis ECSEL JU project. AEx is based on automated exploration of architectures using a flexible and lightweight parallel co-processor template. We compare its current performance in CHStone C-language benchmarks to the state of the art FPGA HLS tool Vitis, provide ASIC implementation numbers, and identify the main remaining toolset features that are expected to dramatically further improve the performance. The potential is explored with a hand-optimized case study that shows only 1.64x performance slowdown with the programmable co-processor in comparison to the fixed function Vitis HLS result.

ASIP
Design space exploration
High-level synthesis
Programmable accelerator overlay
Transport triggered architecture

http://resolver.tudelft.nl/uuid:08f78575-fb81-49ce-b469-c49208269601

https://doi.org/10.1007/s11265-023-01841-3

1939-8018

Journal of Signal Processing Systems: the journal of DSPtechnologies, 95 (9), 1051-1065

Institutional Repository

journal article

© 2023 Alex Hirvonen, Topi Leppänen, Kari Hepola, Joonas Multanen, J.J. Hoozemans, Pekka Jääskeläinen