DTC and TDC IC Design for Ultra-Low-Power ADPLL

Abstract

The technology scaling favors the Digital PLLs, which is reconfigurable. In the traditional fractional-N ADPLL, whether counter-based or divider based, DCO and TDC are the main two power consuming blocks. Modifying the phase detection part based on phase prediction makes the architecture more energy-efficient. The new architecture leads to the first wireless ADPLL breaking 1mW barrier. However, the in-band spurs are very high and DTC gain calibration does not work very well. This thesis proposes a pseudo phase domain model to determine the in-band spur level and validates the accuracy through simulations. It also improves the LMS DTC gain calibration algorithm to solve the problem when FCW fractional part is small DTC gain cannot calibrate correctly. Furthermore, pre-distortion is used to cancel DTC nonlinearity. Apart from theoretically analysis, a first-order $\Sigma-\Delta$ TDC is taped-out, to measure DTC's nonlinearity.