Fully Integrated Analog Front-end for a 2-electrode ECG device

Abstract

Cardiovascular diseases are leading cause of deaths worldwide. With increasing graying population and limited health infrastructure there is a need for portable and implantable ECG devices to diagnose these diseases early on. In general an ECG device requires three or more electrodes, which need to be applied to the body via a gel, to obtain a satisfactory reading. This puts a constraint on the portability of the device. This thesis deals with designing a fully-integrated 10 bit analog front-end i.e. an instrumentation amplifier and an ADC, specifically, for a two-electrode ECG device. Integrated ECG read-out circuits have to deal with two challenges mainly viz. obtaining a high common-mode rejection ratio (CMRR) and integrating large time-constants on the chip. Firstly, all sources of interference which affect an ECG reading is studied. It is shown that for a portable and integrated read-out circuit, a high CMRR is obtained from the fact that the device will be floating and hence the circuit itself need not have a high CMRR. Existing techniques for integrating large time-constants are presented and compared. It is shown that these techniques either give rise to unpredictable time-constants and are non-linear near the required cut-o frequency or consume a lot of power from a system perspective. A novel mixed-signal feedback technique using a sigma-delta ADC has been proposed wherein the digital signal is scaled, integrated and fed back to the previous analog stage. The advantages of such a method are more control over the position of the cut-o frequency and higher linearity. The power consumption needed to implement such a technique is negligible. The circuit is designed in CMOS 0.35um I3T25 technology. The designed instrumentation amplifier reports the best SNR and 3rd highest Noise-Efficieny Factor (NEF). The linearity at the cut-o frequency is shown to be of 10 bits which is an improvement of 3 bits over existing techniques. The total static power consumption for the system is 66uW. The implementation of the time-constant consumes only 40nW of static power.