Experimental analysis of design-for-testability techniques in SRAMs

Abstract

In this thesis the importance of DFTs in the detection of DRFs in embedded SRAMs have been presented. To illustrate their importance an accurate SRAM simulation model has been build. This model was used in the implementation of some existing DFT techniques. The proposed SRAM simulation model includes all peripheral circuits but for the timing generation circuit and the data input and output latch. The advantage of this simulation model is that the model can be used for any simulation purpose concerning memory faults in SRAMs. The addition of the address decoder logic was due to the fact that, the address decoder is necessary when multiple cells has to be accessed in parallel by selecting the appropriate wordlines. This model thus presents a complete analog behavior of an SRAM circuit. However the additional address decoder logic also increases the delay of the SRAM to a greater extend. The evaluation of the WWTM, NWRTM and PDWTM DFT techniques have also provided some data as to how efficient these DFT techniques are thereby easing some design decision as to which DFTs can used in the detecting DRFs in the cell array. Since two of these DFT were proven to detect symmetric and asymmetric faults within a reduced test time, they could be used as standards for the evaluation of other exiting and new DFT techniques. The PDWTM DFT was not validated. However we could not based on the obtained results to draw conclusions. Futher simulations should be carried out. Functional tests most specifically the Pause test was shown to be an inefficient test method in the detection of DFRs since the pause time is very long and not known for small R-values. Using DFTs thus reduces the pause time to a greater extend. DFTs are the most preferred test methods for the detection of DRFs. However the efficiency of any DFT for the detection of DRFs can only be justified if it can detect both symmetric and asymmetric defects, as was the case with two of the DFTs evaluated.