Characterization of waferstepper and process related front- to backwafer overlay errors in bulk micro machining using electrical overlay test structures

Conference paper (2004)
Department
Delft Institute of Microelectronics and Submicron Technologies (EEMCS) (TU Delft)
Copyright: ©2004 Van Zeijl, H.W., Bijnen, F.G.C., Slabbekoorn, J.
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Published Date

16-08-2004

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Source:

Proceedings of SPIE, 2004 vol. 5455

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Delft Institute of Microelectronics and Submicron Technologies

Abstract

To validate the Front- To Backwafer Alignment (FTBA) calibration and to investigate process related overlay errors, electrical overlay test structures are used that requires FTBA [1]. Anisotropic KOH etch through the wafer is applied to transfer the backwafer pattern to the frontwafer. Consequently, the crystal orientation introduces an overlay shift. A double exposure method is presented to separate the process-induced shift from the FTBA shift. The process induced overlay shift can run up to 3µm, large compared to the expected FTBA error (around 0.1 µm). The measured overlay distribution is 0.45 µm (3 ?) this includes both waferstepper and process related overlay errors. The overlay distribution, corrected for waferstepper related overlay errors, like lens distortion, resembles the overlay distribution of the bulk micromachining (BMM) process; 0.26µm (3?). The procedures described in this work provide a quantitative method of describing the waferstepper and process related front to backwafer overlay errors.