Design of a Crypto Core for Securing Intra System-on-Chip Communication

Abstract

Interconnect centric security in multi core System-on-Chip (SoC) is an area of increasing concern. Monitoring and manipulation of the SoC interconnect yields great potential to bypass higher level security mechanisms. This thesis proposes SoC-TLS: a cryptographic hardware solution aimed to protect intra SoC communication against malicious IP and side channel attacks by providing secure - confidential, integer and authenticated - communication channels at the transport layer level of the SoC interconnect. SoC-TLS enhances interconnect (bus/Network-on-Chip) interfaces with a hard crypto core containing enciphering/deciphering and keyed hash functions. This thesis particularly focusses on the design and implementation of an appropriate crypto core to mitigate specific threats concerning intra SoC communication. A lightweight stream cipher and keyed hash function are proposed after a survey of existing stream ciphers and pseudo random number generators. The proposed functions are analyzed to determine their cryptographic strength. Two reference designs are implemented; a single channel design for point-to-point communication and a multichannel design that supports secure connections between 15 secure cores. Implementation results for area and throughput are related to results for Æthereal NoC NI to determine the effects of hypothetical integration.