Realistic Online Resource Management for Partially Reconfigurable Systems

Abstract

In this dissertation, we focus our research on the problems related to efficient configurable resource management for partially reconfigurable systems. FPGA devices are used to build such systems for various application domains with telecommunication and energy efficient high performance computing being two prominent examples. Dynamic management of FPGA hardware resources is an important problem and is the main motivation for this dissertation. Our research starts with investigating an abstract view of configurable resources which represents the essential properties of FPGAs in respect to reconfiguration while leaving out many less important technology details. In this step, a realistic model with adequate complexity is exposed to the configurable resource management algorithms. Next, based on the abstract view, the hardware task's spatial requirements are studied and an efficient online task placement algorithm is proposed. Our placement algorithm dynamically redistributes the reconfigurable resources into blocks with various sizes and outperforms state of the art. In addition, a new model for measuring and analyzing the placement algorithms performance is built. In our next step we take into account also task's temporal requirements and consider holistic online task placement and scheduling. A novel algorithm with support for application specific scheduling heuristics is proposed. In addition, a reuse and partial reuse mechanism is applied to alleviate the single configuration port limitation present in modern systems. After that, a communication model is introduced into the abstract view and the proposed online scheduling algorithm is extended to account the communication paths among data dependent hardware tasks and between tasks and external peripherals. In this step, the complete realistic configurable resource management problem is addressed. Furthermore, mechanisms for hardware reuse and interrupt handling are proposed. The hardware reuse mechanism gives the required hardware support for the reuse and partial reuse mechanisms. The hardware interrupt handling mechanism enables real time applications on reconfigurable systems.