Dry self-alignment for discrete components

Abstract

The assembly of microsystem chips in industrial practices is commonly done by means of a single pick-and-place operation. Despite its high process reliability, this operation is a serial process that cannot compete with the efficiency of the inherent batch-processing capability of the microsystem fabrication. Besides, the speed of a pick-and-place operation often decreases with the increasing placement accuracy. These provide a motivation for the research of a batch-wise-alignment technique, which can be used as an additional means to increase the speed of the pick-and-place operation, or perhaps even as an alternative to replace it. The goal in this research was to investigate and develop a self-alignment technique for the alignment of chips on an intermediate carrier, as such that the chips can be transferred and joined to the target chips by a batch-wise process in the later stage. The self-alignment technique developed in this research employed electrostatic fields in combination with mechanical features. The electrostatic fields were generated between the chips and the carrier by means of charge deposition on the carrier (and the chip). The mechanical features were incorporated on the carrier (and the chip) for two purposes: (1) to prevent a premature sticking of the chip to the charged surface on the carrier; and (2) to ensure alignment and clamping of the chip once it is in the correct position. A mechanical vibration was employed to enhance the chips’ mobility during the alignment. Experimental results proved that self-alignment of chips can be achieved successfully using this technique. The alignment accuracy achieved in the experiments was 3.5 micrometer. However, since the accuracy is a dependant of the mechanical features rather than the alignment process, a better accuracy should be attainable by improving the fabrication tolerance of the mechanical features. It has also been shown experimentally that a unique orientation of the chips in the planar direction can be achieved by placing the mechanical features in asymmetric positions. Furthermore, it has been demonstrated in this research that the chips could be aligned properly even when all the charges and mechanical features were placed only on the carrier. This means that the technique can be applied without necessarily modifying the chips.