Analysis and Design of a 2.5GS/s 6-bit SAR ADC with a 3-bit/cycle Resolving Scheme

Master thesis (2016)

Authors

Contributors

M.A.P. Pertijs (mentor)
Programme
Electronic Instrumentation Laboratory (EEMCS) (TU Delft)
Copyright: © 2016 Ursulean, M.
SAR ADC TI-ADC Analog-to-Digital Converter StrongArm Comparator Asynchronous Capacitive DAC
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Published Date

16-08-2016

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Programme

Electronic Instrumentation Laboratory

Abstract

The thesis analyzes the design challenges that arise when developing high-speed ADCs and shows, through an extensive architecture study, that the SAR topology can be used with a sampling rate of 2.5GS/s if asynchronous processing and a multi-bit per cycle approach are adopted. The transistor-level implementation and simulation of a 6-bit SAR ADC are summarized in order to expose the existing trade-offs in terms of power consumption, speed and area.