Print Email Facebook Twitter Analysis and Design of a 2.5GS/s 6-bit SAR ADC with a 3-bit/cycle Resolving Scheme Title Analysis and Design of a 2.5GS/s 6-bit SAR ADC with a 3-bit/cycle Resolving Scheme Author Ursulean, M. Contributor Pertijs, M.A.P. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics Programme Electronic Instrumentation Laboratory Date 2016-08-16 Abstract The thesis analyzes the design challenges that arise when developing high-speed ADCs and shows, through an extensive architecture study, that the SAR topology can be used with a sampling rate of 2.5GS/s if asynchronous processing and a multi-bit per cycle approach are adopted. The transistor-level implementation and simulation of a 6-bit SAR ADC are summarized in order to expose the existing trade-offs in terms of power consumption, speed and area. Subject TI-ADCADCAnalog-to-Digital ConverterSARStrongArm Comparatorasynchronouscapacitive DAC To reference this document use: http://resolver.tudelft.nl/uuid:041645ca-928a-458b-8729-608c8f1275b7 Embargo date 2021-8-16 Part of collection Student theses Document type master thesis Rights (c) 2016 Ursulean, M. Files PDF MagdaUrsulean_Thesis_Report.pdf 3.91 MB Close viewer /islandora/object/uuid:041645ca-928a-458b-8729-608c8f1275b7/datastream/OBJ/view