A Low Power 10-bit SAR ADC in a 45nm CMOS process

Master thesis (2012)

Authors

Contributors

K.A.A. Makinwa (mentor)
Department
ELlectronic Instrumentation Laboratory (EEMCS) (TU Delft)
Copyright: © 2012 Dyachenko, V.A.
SAR Low power ADC CMOS Low voltage Asynchronous Charge sharing Charge redistributing
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Published Date

02-11-2012

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

ELlectronic Instrumentation Laboratory

Abstract

In this work a low power SAR ADC with 8.9 ENOB for wireless communication systems is presented. A capacitive charge redistribution DAC with a unit capacitor of 0.5fF is used. The implemented charge-sharing technique, allows the use of 2^(N-1) + 1 unit capacitors, instead of the conventional 2^N , thus decreasing the DAC area and the DAC switching power by a factor of 2. An asynchronous digital controller eliminates the need of an external high frequency clock. The test chip has been manufactured in a CMOS 45nm process. The measured power consumption is only 45µW at the sampling rate of 16MS/s. The total area of the ADC is only 0.01mm2 . The achieved FoM of 5.9fJ/conv is comparable with state-of-the art.