60GHz front-end receiver chain in 90nm CMOS technology

Abstract

Operation at millimeter-wave frequency, where up to 7GHz of unlicensed bandwidth is available in the 60GHz band, provides an opportunity to meet the higher data rate demands of wireless users. Advancements in silicon technology permit one to consider exploiting the 60GHz band for commercial applications (e.g., short range, wireless HDTV transmission) for the benefit of end users. This could enable, for example, wireless streaming of uncompressed high-quality video packets of a movie in few seconds due to data rates as high as multi gigabits per second. In this thesis, the design of a receiver front-end circuit for operation in the 60GHz range in 90nm CMOS is described. The thesis includes design details of the blocks used in the receiver, including: quadrature voltage-controlled oscillator (QVCO), local oscillator (LO) buffers, divider chain, low-noise amplifier (LNA) and mixer. The QVCO predicts 56.8-64.8GHz tuning range from schematic simulations. The divider chain has 15GHz locking range at rail-to-rail (0.5V-peak) input signal. The LNA and mixer combination achieves a maximum conversion gain of 26.77dB and a noise figure of 5.88dB. The output -1dB compression point is +6.3dBm and IIP3 is -8.6dBm. The complete front-end consumes 91.7mW from 1V supply. Physical layout of the test circuit and post-layout simulations for the implementation of a test chip including the QVCO and the first stage divider are also presented. Post-layout simulations show a maximum phase noise of -97.4dBc/Hz over 55.4-61.7GHz tuning range.