VHDL to SystemC

The Design of a Translator

Master thesis (2009)

Authors

G.J. Schoneveld

Contributors

T.G.R.M. Van Leuken (mentor)

A.J. Van der Veen (mentor)

Department

Microelectronics & Computer Engineering () (TU Delft)

VHDL Compiler SystemC Converter Translator

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Published Date

27-08-2009

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics & Computer Engineering

Abstract

VHDL and SystemC are both languages to describe or model circuits and systems. Reasons could exist for wanting to translate a model in VHDL to an equivalent model in SystemC. A system in SystemC can be needed for modeling a system with a software part, for a faster simulation, or because some tools only support SystemC. This thesis presents a tool that performs this translation from VHDL to SystemC. The tool is constructed like a regular compiler: It consists of a front-end that reads and analyzes VHDL code and a back-end that generates SystemC code. The front-end came from the FreeHDL project and we have made the back-end ourselves. The back-end generates SystemC code by traversing the tree that comes from the front-end. We have validated that the tool is suitable for simulation purposes and we have verified that the tool translates VHDL without problems in most cases we have seen in the wild.

Files

Thesis.pdf

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