In this paper, development and characterization of a free-standing electroplated copper interconnect for applications in flexible and stretchable electronics is presented. The copper layer with typical thickness of 5 µm is plated into a photoresist mould realizing meander and mesh-like patterns. These are subsequently released resulting in a free-standing electrical interconnect that is optionally conformally coated by a -8 µm thick Parylene N layer. Parylene sealing provides electrical insulation and increases rigidity of the structures. Tensile tests on fabricated samples have shown the elongation capability up to 300% for the mesh design and more than 1000% for the meander design. The Parylene coated samples showed increased rigidity but about 50% reduced elongation. Furthermore, parameterized FEM simulations were performed in order to estimate stress levels for different geometries under tensile stress.@en

The acceptable flexibility for ultra-thin substrate would be reached by embedding the ultra-thin substrate into the flexible polyimide and patterning the poly-silicon or silicon into square/hexagon segmentations. The segments interconnect by metal wires for the signal communication, different wire shapes are designed to reach more flexible. In this contributions, results of FE optimization on mechanical reliability issues of interconnect in-between segments on ultra-thin polyimide/silica rubber substrates are presented. Generation of cracks within the silicon and dielectric layers is then studied under controlled bending (glass cylinders with diameters of 2 - 10 mm, compressive and tensile stress) using specially for this purpose designed bending tools. Specimen observation is done using an optical microscope with possibility of digital recording and evaluation by pattern recognition software. The results show that the cracks appear first in the dielectric layers in-between the silicon layer segments and only at higher loads propagate or are generated within the silicon itself. The development of first cracks depends significantly on the silicon layer segmentation size which affects both the crack density and the crack width. The crack density increases sharply with the strain for early stage and then increases slightly. The crack width increases steadily. The high flexibility result can be reached that no crack be detectd under the bending tests with 2 mm diameters. Multilevel FEM simulations are performed in order to increase understanding of the major failure processes. Results of simulations and experiments compare quite well. Second generation samples are designed with consideration of interconnect in-between segments and avoid of silicon dioxide in-between segments.@en