We are developing a kilo-pixels Ti/Au TES array as a backup option for Athena X-IFU. Here we report on single-pixel performance of a 32 × 32 array operated in a Frequency Division Multiplexing (FDM) readout system, with bias frequencies in the range 1-5 MHz. We have tested the pixels response at several photon energies, by means of a 55Fe radioactive source (emitting Mn-Kα at 5.9 keV) and a Modulated X-ray Source (MXS, providing Cr-Kα at 5.4 keV and Cu-Kα at 8.0 keV). First, we report the procedure used to perform the detector energy scale calibration, usually achieving a calibration accuracy better than ∼0.5 eV in the 5.4-8.9 keV energy range. Then, we present the measured energy resolution at the different energies (best single pixel performance: ΔEFWHM = 2.40 ± 0.09 eV @ 5.4 keV; 2.53 ± 0.10 eV @ 5.9 keV; 2.78 ± 0.16 eV @ 8.0 keV), investigating also the performance dependency from the pixel bias frequency and the count rate. Thanks to long background measurements (∼1 d), we finally detected also the Al-Kα line at 1.5 keV, generated by fluorescence inside the experimental setup. We analyzed this line to obtain a first assessment of the single-pixel performance also at low energy (ΔEFWHM = 1.91 eV ± 0.21 eV @ 1.5 keV), and to evaluate the linearity of the detector response in a large energy band (1.5-8.9 keV). @en

Immersed gratings offer several advantages over conventional gratings: more compact spectrograph designs, and by using standard semiconductor industry techniques, higher diffraction-efficiency and lower stray-light can be achieved. We present the optical tests of the silicon immersed grating demonstrator for the Mid-infrared E-ELT Imager and Spectrograph, METIS. We detail the interferometric tests that were done to measure the wavefront-error and present the results of the throughput and stray-light measurements. We also elaborate on the challenges encountered and lessons learned during the immersed grating demonstrator test campaign that helped us to improve the fabrication processes of the grating patterning on the wafer. @en