In this paper, the interaction between chip and package is investigated with the focus on low ppm-level failures. More specifically, the failure mode of inter-metal shorts is investigated, caused by either electrical discharges (ESD) or internal/external mechanical forces. It is demonstrated that forces induced by the filler particles in the molding compound can cause these shorts. Finite element simulations are performed in order to estimate the stress levels in the backend stack of the integrated circuit (IC). Nano-indentation experiments are performed to measure the hardness of different passivation materials. The simulation and indentation results are combined with estimations and measurements of the particle size distribution, flow modeling and statistical methods. As such, the ppm-level of the failures could be attributed to the low chance that a filler particle would land on the critical location. Measures to prevent these failures are to be found in the area of improved passivation materials and/or recipes in combination with other molding compounds. For succesful development of IC backend structures and processes, it is essential to take into account the influence of the package in the earlier phase of IC backend development.@en

The first part of this paper deals with the analysis of layer buckling and delamination of thin film multilayer structures that are used in flexible display applications. To this end, 250 nm thick indium tin oxide (ITO) layers have been deposited on a 200 µm thick high temperature aromatic polyester substrate (Arylite) with a 3 µm silica-acrylate hybrid hard coat (HC). Typical buckle morphologies are determined from two-point bending experiments, in which geometries are measured after straightening of the sample. Finite element simulations have been performed to estimate the corresponding interface properties and compressive strains in the layers, and to illustrate the effect of sample straightening on the buckle geometry. The second part considers the fracture sensitivity analysis of an active matrix Thin Film Transistor (TFT) display containing 512 x 256 pixels, with a typical pixel dimension of 160 x 160 µm. Due to the large scale differences between the display and the TFT patterning a multi-scale modelling framework has been developed, which allows to include realistic material stacks and a detailed pixel geometry. The resulting patterning effect shows an anisotropic behaviour at both the pixel level and the global display level due to the multi-scale approach. Using the Area Release Energy (ARE) method an energy-based failure criterion has been utilised to analyse cohesive failure at several (critical locations in the pixel geometry. Specifically, the sensitivity to tunnelling cracks in the dielectric layers is considered, which have been experimentally observed in comparable TFT samples that are subjected to tension. This local failure analysis allows for the identification of critical regions within the pixel geometry, which strongly depend on the location within a pixel.@en

The mechanical response at the interface between the silicon, low-k and copper layer of the wafer is simulated herein under the loading of the chemical-mechanical polishing (CMP). To identify the possible generation/propagation of the initial crack, the warpage induced by the thin-film fabrication process are considered, and applying pressure, status of slurry and the copper thickness are treated as the parameter in the simulation. Both the simulation and experimental results indicate that the large blanket wafer within high applying pressure would exhibit high stresses possible to delaminate the interface at the periphery of the wafer, and reducing the copper thickness can diminish the possibility of the delamination/failure of the low-k material.@en

For integrated circuit (IC) wafer back-end development, state-of-the-art CMOS-technologies have to be developed and robust bond pad structures have to be designed in order to guarantee both functionality and reliability during waferfab processes, packaging, qualification tests, and, of course, usage. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures. However, bad thermal and mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back-end structure when no appropriate precautions are taken. This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the Area Release Energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy-based, thus more accurate than stress-based criteria; (3) unlike recent fracture mechanics approaches, no initial defect size and location has to be assumed a priori. A mesh objectivity condition is formulated resulting from numerical experiments. The method is applied to advanced IC back-end structures, revealing not only the most critical back-end design but also the critical interfaces in the bond pad structures at which delamination might occur. In order to bridge the length scale difference between the wafer level and the back-end structures, a multi-scale method has been implemented in the finite element code MSC.Marc. In this way, effects of e.g., packaging and wire bond loading at the global level can be studied while taking into account the possibility of occurring failure phenomena at the local, back-end level. The validity and applicability of the method will be demonstrated by considering several Cu/low-k back-end structures. The obtained results are in good agreement with experimental observations.@en

The first part of this paper deals with the analysis of layer buckling and delamination of thin film multi-layer structures that are used in flexible display applications. To this end, 250 nm thick indium tin oxide (ITO) layers have been deposited on a 200 µm thick high temperature aromatic polyester substrate (Arylite¿) with a 3 µm silica-acrylate hybrid hard coat (HC). Typical buckle morphologies are determined from two-point bending experiments, in which buckle widths and heights are measured after straightening of the sample. Finite element simulations have been performed to estimate the corresponding interface properties and compressive strains in the layers, and to illustrate the effect of sample straightening on the buckle geometry. The second part considers the fracture sensitivity analysis of an active matrix Thin Film Transistor (TFT) display containing 512 x 256 pixels, with a typical pixel dimension of 160 x 160 µm. Due to the large scale differences between the display and the TFT patterning a multi-scale modelling framework has been developed, which allows to include realistic material stacks and a detailed pixel geometry. The resulting patterning effect shows an anisotropic behaviour at both the pixel level and the global display level due to the multi-scale approach. Using the Area Release Energy (ARE) method an energy-based failure criterion has been utilised to analyse cohesive failure at several (critical) locations in the pixel geometry. Specifically, the sensitivity to tunnelling cracks in the dielectric layers is regarded, which have been experimentally observed in comparable TFT samples that are subjected to tension. This local failure analysis allows for the identification of critical regions within the pixel geometry, which strongly depend on the location.@en