TS

T Suligoj

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20 records found

FinFET Considerations for 0.18 um Technology
Conference paper - V. Jovanovic, M Poljak, T Suligoj

Quantum-mechanical modeling of phonon-limited electron mobility in bulk MOSFETS, ultrathin-body SOI MOSFETS and double-gate MOSFETS for different orientations
Conference paper - M Poljak, V. Jovanovic, T Suligoj

Physical mechanisms of electron mobility behavior in ultra-thin body double gate MOSFETS with (100) and (111) active surfaces
Conference paper - M Poljak, V. Jovanovic, T Suligoj

Optimization of the perimeter doping of ultrashallow p+-n¿-n+ photodiodes
Conference paper - T Knezevic, T Suligoj, A. Sakic, L.K. Nanver

Improving bulk FinFET DC performance in comparison to SOI FinFET
Journal article - M Poljak, V. Jovanovic, T Suligoj

Features of electron mobility in ultrathin-body InGaAs-on-insulator MOSFETs down to body thickness of 2 nm
Conference paper - M Poljak, V. Jovanovic, T Suligoj

1.9 nm Wide Ultra-High Aspect-Ratio Bulk-Si FinFETs

FinFET technology for wide-channel devices with ultra-thin silicon body

Vertical silicon-on-nothing FET: subthreshold slope calculation using compact capacitance model
Journal article - B Svilicic, V. Jovanovic, T Suligoj

Compact Capacitance Model for Drain-Induced Barrier-Lowering of Vertical SONFET
Conference paper - B Svilicic, V. Jovanovic, T Suligoj

Modeling study on carrier mobility in ultra thin body FinFETS with circuit level implications
Conference paper - M Poljak, V. Jovanovic, T Suligoj

Sub-100 nm silicon-nitride hard-mask for high aspect-ratio silicon fins

Quantum Confinement and Scaling Effects in Ultra-Thin Body Double-Gate FinFETs
Conference paper - M Poljak, V. Jovanovic, T Suligoj

Vertical silicon-on-nothing FET: threshold voltage calculation using compact capacitance model
Journal article - B Svilicic, V. Jovanovic, T Suligoj

Vertical Silicon-on-Nothing FET: Capacitance-Voltage Compact Modeling
Conference paper - B Svili¿i¿, V Jovanovi¿, T Suligoj

Physics-based modeling of hole mobility in ultrathin-body silicon-on-insulator MOSFETs
Conference paper - M Poljak, V. Jovanovic, T Suligoj

Application of spacer hard-masks for sub-100 nm wide silicon fin-etching

Vertical Silicon-on-Nothing FET: Analytical Model of Subthreshold Slope
Conference paper - B Svili¿i¿, V Jovanovi¿, T Suligoj

Suppression of corner effects in wide channel triple gate bulk finfets
Journal article - M Poljak, V. Jovanovic, T Suligoj

Analysis of subthreshold conduction in short channel recessed source/drain UTB SOI MOSFETs
Journal article - B Svilicic, V. Jovanovic, T Suligoj