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document
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Chen, Y. (author), Gong, J. (author), Staszewski, R.B. (author), Babaie, M. (author)
In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the...
journal article 2022
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document
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Gong, J. (author), Chen, Y. (author), Charbon-Iwasaki-Charbon, E. (author), Sebastiano, F. (author), Babaie, M. (author)
This article presents a 4-to-5GHz LC oscillator operating at 4.2K for quantum computing applications. The phase noise (PN) specification of the oscillator is derived based on the control fidelity for a single-qubit operation. To reveal the substantial gap between the theoretical predictions and measurement results at cryogenic temperatures, a...
journal article 2022
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document
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Chen, Peng (author), Huang, Xiongchuan (author), Chen, Y. (author), Wu, Lianbo (author), Staszewski, R.B. (author)
To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order ΔΣ time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A...
journal article 2018
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