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document
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Van Straten, J. (author)
This thesis describes the design and implementation of a VLIW processor and associated caches based on the ρ-VEX concept. An ρ-VEX processor must be dynamically (runtime) reconfigurable to behave as a single large processor, two medium-sized processors, or four small processors. This allows a scheduler to optimize for energy and/or performance...
student report 2016
Source URL (retrieved on 2024-04-28 06:27): https://repository.tudelft.nl/islandora/search/subject%3A%22%255C%253F%255C-VEX%22?collection=education&f%5B0%5D=mods_name_personal_author_namePart_family_ss%3A%22Van%5C%20Straten%22