An Efficient In-Memory Computing Architecture for Image Enhancement in AI Applications

Journal Article (2022)
Author(s)

Meriem Bettayeb (Khalifa University of Science and Technology)

Fakhreddine Zayer (Khalifa University of Science and Technology)

Heba Abunahla (Khalifa University of Science and Technology)

Gabriele Gianini (Khalifa University of Science and Technology, University of Milan)

Baker Mohammad (Khalifa University of Science and Technology)

Affiliation
External organisation
DOI related publication
https://doi.org/10.1109/ACCESS.2022.3171799 Final published version
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Publication Year
2022
Language
English
Affiliation
External organisation
Journal title
IEEE Access
Volume number
10
Pages (from-to)
48229-48241
Downloads counter
11

Abstract

Random spray retinex (RSR) is an effective image enhancement algorithm owing to its effectiveness in improving the image quality. However, the computing complexity of the algorithm, the required hardware resources, and memory access hamper its deployment in many application scenarios, for instance, in IoT systems with limited hardware resources. With the rise of artificial intelligence (AI), the use of image enhancement has become essential for improving the performance of many emerging applications. In this paper, we propose the use of RSR as a preprocessing filter before the task of semantic segmentation of low-quality urban road scenes. Using the publicly available Cityscapes dataset, we compared the performance of a pre-trained deep semantic segmentation network on dark and noisy images with that of RSR preprocessed images. Our findings confirm the effectiveness of RSR in improving segmentation accuracy. In addition, to address the computational complexity and suitability of edge devices, we propose a novel and efficient implementation of RSR using resistive random access memory (RRAM) technology. This architecture provides highly parallel analog in-memory computing (IMC) capabilities. A detailed, efficient, and low-latency implementation of RSR using RRAM-CMOS technology is described. The design was verified using SPICE simulations with measured data from the fabricated RRAM and 65 nm CMOS technologies. The approach presented here represents an important step towards a low-complexity, real-time hardware-friendly architecture and the design of retinex algorithms for edge devices.