WideBand PLL as a clock multiplier

Abstract

In this study, the theory, design and analysis of PLL circuits are examined and a 4.9GHz ~ 5.9GHz Wideband CMOS PLL Frequency Synthesizer is designed and implemented in IBM 65nm digital-process. The objective of this thesis work is to understand the limitations in Wideband PLL systems when the application frequency range extends to multiple gigahertz. This study explores the inband noise contribution of PLL blocks and also investigates solutions to high frequency operation of phase frequency detectors and charge pumps. A high frequency phase-frequency detector topology is presented. With this topology, static phase error of the loop remains close to zero even if the charge-pump has a large amount of current mismatch. A design which is capable correct operation up to a frequency 1.74 GHz is designed. A high frequency differential charge pump circuit with glitch suppression is presented. The VCO of the PLL is implemented with a mutlipath loop ring oscillator. The VCO has a better supply noise performance compared to conventional ring oscillators but however it is still not suitable for applications with noisy supply, thus off chip supply decoupling is used. VCO operates within 4.79GHz ~ 6.54GHz for all process corners. The frequency divider which is used from project library has a constant division ratio of 6. Entire PLL design consumes 14.9 mW from 1.2 V supply, under typical conditions. Total area of the PLL is 1 mm x 800 um including the pads.