A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

Conference Paper (2018)
Author(s)

Min-Shueh Yuan (Taiwan Semiconductor Manufacturing Company (TSMC))

Chao-Chieh Li (Taiwan Semiconductor Manufacturing Company (TSMC))

Chia-Chun Liao (Taiwan Semiconductor Manufacturing Company (TSMC))

Y. Lin (Taiwan Semiconductor Manufacturing Company (TSMC))

Chih-Hsien Chang (Taiwan Semiconductor Manufacturing Company (TSMC))

RB Staszewski (University College Dublin)

Affiliation
External organisation
DOI related publication
https://doi.org/10.1109/ISSCC.2018.8310377
More Info
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Publication Year
2018
Language
English
Affiliation
External organisation
Volume number
61
Pages (from-to)
448-450
ISBN (electronic)
978-1-5090-4940-0

Abstract

The current paradigm of frequency synthesis for short-range wireless transceivers, such as BLE, is to use a crystal oscillator (XO) in the tens-of-MHz range as a frequency reference (FREF) to phase lock an RF oscillator [1-4]. This ensures a sufficiently wide PLL bandwidth of tens to hundreds of kHz to quickly acquire a new channel and to suppress lower-frequency phase noise (PN) of the RF oscillator. The latter requirement can be alleviated by substantially lowering the flicker PN of a digitally controlled oscillator (DCO) thus allowing to freeze its tuning word updates during receive (RX) packets and further directly FM-modulating the DCO during transmit (TX) packets [1]. However, an all-digital PLL (ADPLL) is still needed just to quickly settle the DCO to each new channel.

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