Towards CMOS Bulk Sensing for In-Situ Evaluation of ALD Coatings for Millimeter Sized Implants

Abstract

To meet the dimensional requirements for bioelectronic medicine, new packaging solutions are needed that could enable small, light-weight and flexible implants. For protecting the implantable electronics against biofluids, recently various atomic layer deposited (ALD) coatings have been proposed with high barrier properties. Before implantation, however, the protective coating should be evaluated for any defects which could otherwise lead to leakage and device failure. In these cases, the conventional helium leak test method can no longer be used due to the millimeter size of the implant. Therefore, an in-situ sensing platform is needed that could evaluate the coating and justify the implantation of the final device. In this work, we explore the possibility of using the CMOS bulk for such a platform. Towards this aim, as a proof of concept, test chips were made in a standard 6-metal 0.18 μm CMOS process and for the connection to the bulk, a p+ diffusion was used. A group of samples was then coated with an ALD multilayer. For coating evaluation, off-chip DC current leakage and impedance measurements were carried out in saline between the CMOS bulk and a platinum reference electrode. Results were compared between non-coated and coated chips that clearly demonstrated the potential of using the bulk as a sensing platform for coating evaluations. This novel approach could pave the way towards an all integrated in-situ hermeticity test, currently missing in mm-size implants.