Hardware-Aware Energy Estimator pipeline for µNAS
M. Šmitas (TU Delft - Electrical Engineering, Mathematics and Computer Science)
H. Liu – Mentor (TU Delft - Electrical Engineering, Mathematics and Computer Science)
M.A. Zuñiga Zamalloa – Mentor (TU Delft - Electrical Engineering, Mathematics and Computer Science)
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Abstract
Running deep learning models directly on microcontroller units (MCUs)—a field known as TinyML—enables artificial intelligence in energy-restricted applications that rely strictly on limited battery power or harvested local energy. Creating models for these constrained devices requires strict optimization via neural architecture search (NAS) frameworks such as µNAS. However, traditional proxies like multiply-accumulate (MAC) counts fail to serve as accurate energy predictors because they overlook complex hardware interactions and compiler-level runtime optimizations introduced by deployment engines such as TensorFlow Lite (TFLite) Micro.
In this paper, we explore accurate energy estimation within the µNAS framework. We build an automated hardware-in-the-loop (HIL) profiling pipeline to deploy diverse architectures on an MCU and record their physical power draw, generating a dataset of 671 unique models. Evaluating a baseline linear regression predictor applied to MAC counts achieves a high macro-level fit (R² = 0.985) but suffers from an unacceptable mean absolute percentage error (MAPE) of 85.4% due to structural oversights.
To address this limitation, we propose a novel energy estimator based on a directed acyclic graph neural network (DAGNN). By processing neural network topology directly, the DAGNN learns complex hardware interactions and runtime optimization behaviors. Our estimator substantially outperforms the baseline, reducing MAPE from 85.4% to 16.0%.