Understanding MPSoCs

Exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs

Conference paper (2018)

Authors

Johanna Sepulveda Technische Universität München
Cezar Reinbrecht Computer Engineering - EEMCS
Siavoosh Payandeh Azad Tallinn University of Technology
Behrad Niazmand Tallinn University of Technology
Gert Jervan Tallinn University of Technology
Research Group
Computer Engineering (EEMCS) (TU Delft)
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Published Date

15-07-2018

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

Multi-Processor Systems-on-Chips (MPSoCs) are the key enabler technology for current and future applications. However, the high on-chip connectivity, the programmability and IPs reusability, also introduce security concerns. Problems arise when applications with different trust and security levels share the MPSoC resources. One of the potent threats that MPSoCs see themselves exposed to are the so-called side-channel attacks (SCA). In this work, we explore the cache-based side-channel attacks optimized by the communication structure. We evaluate the vulnerability of the different NoC-based MPSoC memory configuration against micro-architectural side channel attacks. Our attack targets an MPSoC AES T-Table implementation. We explore the impact of the MPSoC organization on the NoC timing attack. We present the huge impact on the memory organization and present two attack metrics: efficacy and efficiency. Our results show that NoC-based MPSoCs are vulnerable and that deep memory hierarchies favor the security of the system.