Pauli Frames for Quantum Computer Architectures

Conference Paper (2017)
Author(s)

Leon Riesebos (TU Delft - FTQC/Bertels Lab)

Xiang Fu (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Savvas Varsamopoulos (TU Delft - FTQC/Bertels Lab)

Carmina García Almudever (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Koen Bertels (TU Delft - FTQC/Bertels Lab, TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group
FTQC/Bertels Lab
DOI related publication
https://doi.org/10.1145/3061639.3062300 Final published version
More Info
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Publication Year
2017
Language
English
Research Group
FTQC/Bertels Lab
Article number
76
Pages (from-to)
1-6
ISBN (electronic)
978-1-4503-4927-7
Event
54th Annual Design Automation Conference, DAC 2017 (2017-06-18 - 2017-06-22), Austin, United States
Downloads counter
245

Abstract

The Pauli frame mechanism allows Pauli gates to be tracked in classical electronics and can relax the timing constraints for error syndrome measurement and error decoding. When building a quantum computer, such a mechanism may be beneficial, and the goal of this paper is not only to study the working principles of a Pauli frame but also to quantify its potential effect on the logical error rate. To this purpose, we implemented and simulated the Pauli frame module which, in principle, can be directly mapped into a hardware implementation. Simulation of a surface code 17 logical qubit has shown that a Pauli frame can reduce the error rate of a logical qubit up to 70% compared to the same logical qubit without Pauli frame when the decoding time equals the error correction time, and maximum parallelism can be obtained.