Logical-to-Physical Compilation for Reducing Depth in Distributed Quantum Systems

Conference Paper (2026)
Author(s)

F.W.M. de Ronde (TU Delft - Electrical Engineering, Mathematics and Computer Science)

J.S.S.M. Wong (TU Delft - Electrical Engineering, Mathematics and Computer Science)

S. Feld (TU Delft - QCD/Feld Group, TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group
Computer Engineering
DOI related publication
https://doi.org/10.1109/ICCCN69946.2026.11662592 Final published version
More Info
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Publication Year
2026
Language
English
Research Group
Computer Engineering
Publisher
IEEE
ISBN (print)
979-8-3315-6414-8
ISBN (electronic)
979-8-3315-6413-1
Event
2026 35th International Conference on Computer Communications and Networks (ICCCN) (2026-07-27 - 2026-07-30), Honolulu, United States
Page Views
34
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Abstract

Quantum computing is expected to become a foundational technology for solving problems that exceed the capabilities of classical systems. As quantum algorithms and hardware technologies continue to advance, the need for scalable architectures becomes increasingly clear. Distributed quantum computing offers a promising path forward by interconnecting multiple smaller processors into a larger, more powerful system. However, distributed quantum computing introduces significant circuit depth overhead, as logical operations are typically decomposed into sequential physical procedures that require entanglement generation. These sequential operations limit the reliability of quantum algorithms in the NISQ era due to noise. In this work, we present a compiler that integrates logical-to-physical decomposition with depth-aware rescheduling to reduce the execution cost of distributed quantum circuits. The compiler identifies sequences of logical CNOT gates that share a control or target qubit, reschedules them into parallel instruction groups, and applies decompositions that allow multiple gates to be executed simultaneously using distributed shared entanglement resources. An algorithm is proposed that ensures parallelism is created when possible while keeping logical equivalence and that circuit depth is never increased. Benchmark results demonstrate that the compiler consistently reduces circuit depth for circuits containing inherently sequential CNOT structures, while leaving already-parallel circuits unchanged. These results highlight the value of combining scheduling and hardware-aware decomposition, and establish the compiler as a practical tool for improving the fidelity of distributed quantum computations.

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