An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology

Conference paper (2016)

Authors

D.G. Muratore Pavia University

Alper Akdikmen Pavia University

Edoardo Bonizzoni Pavia University

Franco Maloberti Pavia University

U. Fat Chio University of Macau

Sai Weng Sin University of Macau

Rui Paulo Martins University of Macau

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Published Date

2016

Language

English

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Abstract

This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm2 and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.