An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop
Peng Chen (University College Dublin)
Xiongchuan Huang (Broadcom)
Y. Chen (TU Delft - Electronics)
Lianbo Wu (ETH Zürich)
Bogdan Staszewski (University College Dublin)
More Info
expand_more
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Abstract
To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order ?? time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A system self-calibration algorithm is proposed to calibrate nonlinearities of the analog circuitry. The operation is robust over PVT variations since the delay information is normalized to the input clock period. To verify the proposed idea, two different digital-to-time converters performing the on-chip delay are measured and analyzed at 50-MHz clocking frequency with 0.65-ps standard time deviation per measurement.
help_outline