A new methodology in power estimation in CMOS combinational circuits at logic level (U-SP-2-I-ICT)
Conference Paper
(2006)
Author(s)
AL Aita (TU Delft - Electronic Instrumentation)
LL De Oliveira (External organisation)
JP Dos Santos Martins (External organisation)
Research Group
Electronic Instrumentation
To reference this document use:
https://resolver.tudelft.nl/uuid:710536db-0b00-4e15-8212-956c42047db4
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Publication Year
2006
Research Group
Electronic Instrumentation
Pages (from-to)
1127-1130
ISBN (print)
0-7803-9197-7
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