A pipeline ADC for very high conversion rates

Conference paper (2016)

Authors

D.G. Muratore Pavia University
Edoardo Bonizzoni Pavia University
Franco Maloberti Pavia University
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Published Date

2016

Language

English

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Abstract

This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.