A pipeline ADC for very high conversion rates

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A pipeline ADC for very high conversion rates

Conference Paper (2016)

Author(s)

Dante Gabriel Muratore (Università di Pavia)

Edoardo Bonizzoni (Università di Pavia)

Franco Maloberti (Università di Pavia)

DOI related publication

https://doi.org/10.1109/ISCAS.2016.7527529 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:73b4e375-004b-480a-9e4d-983d29c3e6f0

More Info

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Publication Year

2016

Language

English

Article number

7527529

Pages (from-to)

1446-1449

ISBN (electronic)

9781479953400

Event

Downloads counter

89

Abstract

This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.