A 3.5–6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

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A 3.5–6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

Conference Paper (2016)

Author(s)

Y Wu (TU Delft - Electronics)

Mina Shahmohammadi (TU Delft - Electronic Components, Technology and Materials)

Yue Chen (TU Delft - Electronics)

Ping Lu (Lund University)

Robert Bogdan Staszewski (University College Dublin, TU Delft - Electronics)

Research Group

Electronics

DOI related publication

https://doi.org/10.1109/ESSCIRC.2016.7598279

DTC Delta-sigma modulation Noise shaping Oscillators Phase noise TDC Tuning ADPLL Jitter Jitter Wide-bandwidth Delays DCO Phase noise BBPD Phase locked loops Digital phase locked loops Size 40 nm Frequency measurement MASH Digital-to-time converter Integrated circuit noise Time-digital conversion DTC-assisted fractional-N all-digital PLL MASH ?S TDC Frequency 1.73 GHz to 3.38 GHz Frequency 3.5 GHz to 6.8 GHz Integrated jitter Low-in-band phase noise Power 10.7 mW Wide-tuning range DCO Wide-tuning range digitally-controlled oscillator Multi-stage noise shaping All digital PLL Wide-tuning range

To reference this document use:

https://resolver.tudelft.nl/uuid:74e79b80-6a13-495b-ab53-d26aef221782

More Info

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Publication Year

2016

Language

English

Research Group

Electronics

Pages (from-to)

209-212

ISBN (print)

978-1-5090-2973-0

ISBN (electronic)

978-1-5090-2972-3

Abstract

We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fsrms integrated jitter.

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