On-line testing of routers in networks-on-chip

Abstract

Due to recent progress in semiconductor technology, communication is becoming the major source of expense in today's chip design. Network-on-Chip (NoC) is a new paradigm for solving the problem of complex communication on the chips. However, in order to NoC to be ecient in providing complex on-chip communication, the designers should be assured about its correct functionality. For this reason, an ecient test method should be developed for testing the NoC. In order to test the NoC in an ecient way, the test method should be in a way that does not degrade the performance of the NoC (with online test). Moreover it should test the NoC with a high fault coverage (structural test). In this thesis, a new platform is proposed to do online-structural test on NoC. Although NoC's elements has been tested after manufacturing and before being used in a SoC, but when NoC is being used, after some time there is possibility that some errors occur in the elements (e.g. router) of NoC and ruin their functionality. The proposed platform, helps the system developers with online detection and localization of the errors that may occur in routers. Therefore, it increases NoC's reliability. In this platform, the idle routers of NoC are being tested while the rest of the routers are providing on-chip communication. For testing the router the standard test architecture for testing embedded cores (Test-Access-Mechanism (TAM), wrapper, source and sink)is used. In this architecture it is assumed that source and sink are given. The main contribution of this project is to design the wrapper element in such a way that it can be used in the proposed online-structural test platform and reuse NoC as TAM. The limitation of the proposed method is that the number of routers that can be tested at the same time without interrupting NoC's normal functionality depends on topology and size of the NoC. The major cost of this test methods, is related to the wrapper architecture.