Cryogenic Circuit Performance Prediction Using Design-Oriented Model (SEKV) On 22nm FDSOI

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Cryogenic Circuit Performance Prediction Using Design-Oriented Model (SEKV) On 22nm FDSOI

Conference Paper (2025)

Author(s)

Brian Martinez (Université Grenoble Alpes)

Hung-Chi Han (École Polytechnique Fédérale de Lausanne)

FlávioE Bergamaschi (Université Grenoble Alpes)

Quentin Schmidt (CEA-Leti, Grenoble Alpes University)

Antoine Faurie (Université Grenoble Alpes)

Edoardo Charbon (École Polytechnique Fédérale de Lausanne)

Yvain Thonnart (Université Grenoble Alpes)

Baptiste Jadot (Université Grenoble Alpes)

Xavier Jehl (Université Grenoble Alpes)

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DOI related publication

https://doi.org/10.1109/iscas56072.2025.11043615 Final published version

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https://resolver.tudelft.nl/uuid:7fb92849-6281-400c-b55b-c2695010b8c9

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Publication Year

2025

Language

English

Affiliation

External organisation

Publisher

IEEE

ISBN (electronic)

9798350356830

Downloads counter

144

Abstract

This paper demonstrates the design process and performance prediction of a cryogenic 22 nm FDSOI circuit using a design-oriented model. The simplified EKV model is adopted to capture IV characteristics of short-channel transistors, for which parameters are extracted from cryogenic measurement of commercial FDSOI MOSFETs. When applied to a complete circuit, the model accurately predicts performances at various back-gate voltages and temperatures, achieving less than 1 % average absolute error. This validates the presented analytical approach, even under the stringent requirements of low-temperature operation, paving the way to exploiting rather than enduring cryogenic temperature effects on CMOS designs.