Test Set Development for Cache Memory in Modern Microprocessors

Journal article (2008)

Authors

Z. Al-Ars

S. Hamdioui

G. Gaydadjiev

S. Vassiliadis

Department

Microelectronics & Computer Engineering () (TU Delft)

Memory testing Fault coverage Microprocessor cache Test set development Test time

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http://resolver.tudelft.nl/uuid:7fc93845-cd3a-4339-90e1-6411fe183d67

Published Date

08-06-2008

Reuse Rights

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Source:

IEEE Transactions on Very Large Scale Integration, 16 (6), 2008

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics & Computer Engineering

Abstract

Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transistors dedicated to such memories. This paper discusses the methodology used to develop effective and efficient cache tests, and the way it is implemented to optimize the test set used at Intel to test their 512-kB caches manufactured in a 0.13- mtechnology. An example is shown where a maximal test set of 15 tests with a corresponding maximum test time of 160.942 ms/chip is optimized to only six tests that require a test time of only 30.498 ms/chip.

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