A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter with Digital Calibration

Journal article (2016)

Authors

Ping Lu Lund University
Y. Wu Electronics - EEMCS
Pietro Andreani Lund University
Research Group
Electronics (EEMCS) (TU Delft)
Time-to-digital converter (TDC) Gated ring oscillator (GRO) Two-dimensional (2-D) Vernier
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Published Date

2016

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

This brief presents a two-dimensional (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated ring oscillators (GROs) in the X/Y Vernier branches. The already small Vernier quantization noise (∼10.6 ps) is improved by the first-order noise shaping of the GRO. Moreover, since all the delay differences between the X and Y phases can be used (rather than only the diagonal line of the one-dimensional architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65-nm CMOS process and consumes 2.3 mA from 1.0 V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2 ps, whereas the average latency time (within 2 ns) is less than 1/6 of that in a standard Vernier TDC.