A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

Conference Paper (2017)
Author(s)

FW Kuo (Taiwan Semiconductor Manufacturing Company (TSMC))

Seyednaser Pourmousavian (University College Dublin)

Teerachot Siriburanon (University College Dublin)

Huan-Neng (Ron) Chen (Taiwan Semiconductor Manufacturing Company (TSMC))

L Cho (Taiwan Semiconductor Manufacturing Company (TSMC))

Chewn-Pu Jou (Taiwan Semiconductor Manufacturing Company (TSMC))

Fu-Lung Hsueh (Taiwan Semiconductor Manufacturing Company (TSMC))

RB Staszewski (University College Dublin)

Affiliation
External organisation
DOI related publication
https://doi.org/10.23919/VLSIC.2017.8008472
More Info
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Publication Year
2017
Language
English
Affiliation
External organisation
Pages (from-to)
C178-C179
ISBN (print)
978-4-86348-606-5
ISBN (electronic)
978-4-86348-614-0

Abstract

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86ps while dissipating only 1.6mW at 40 MHz reference. The power consumption reduces to 0.8 mW during BLE transmission when the DCO switches to open-loop.

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