FASTER

Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

Journal article (2015)

Authors

Dionisios Pnevmatikatos Foundation for Research and Technology - Hellas (FORTH)

K. Papadimitriou Foundation for Research and Technology - Hellas (FORTH)

W Luk Imperial College London

Xinyu Niu Imperial College London

I. Papaefstathiou Synelixis Solutions

D. Pau STMicroelectronics

Oliver Pell Maxeler Technologies

Christian Pilato Politecnico di Milano

M. D. Santambrogio Politecnico di Milano

D. Sciuto Politecnico di Milano

D. Stroobandt Universiteit Gent

Tim Todman Imperial College London

T. Becker Imperial College London

Elias Vansteenkiste Universiteit Gent

P. Böhm Imperial College London

A. Brokalakis Synelixis Solutions

K. Bruneel Universiteit Gent

C. Ciobanu Chalmers University of Technology

T. Davidson Universiteit Gent

G. Gaydadjiev Chalmers University of Technology

K. Heyse Universiteit Gent

Affiliation

External organisation

Verification Dynamic reconfiguration Micro-reconfiguration Partial reconfiguration Reconfigurable computing Runtime system

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Published Date

31-05-2015

Language

English

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Affiliation

External organisation

Abstract

Abstract The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) EU FP7 project, aims to ease the design and implementation of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving high performance and extending product functionality and lifetime via the addition of new features that operate at hardware speed. However, designing a changing hardware system is both challenging and time-consuming. FASTER facilitates the use of reconfigurable technology by providing a complete methodology enabling designers to easily specify, analyze, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. Our tool-chain supports both coarse- and fine-grain FPGA reconfiguration, while during execution a flexible run-time system manages the reconfigurable resources. We target three applications from different domains. We explore the way each application benefits from reconfiguration, and then we asses them and the FASTER tools, in terms of performance, area consumption and accuracy of analysis.