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A silicon MEMS structure for characterization of femto-farad-level capacitive sensors with lock-in architecture

Journal article (2010)
Department
DIMES
Copyright: ©2010 Wei, J., Chen, Z.L., Liu, Z.W., Sarro, P.M., Institute of Physics
DOI: https://doi.org/doi:10.1088/0960-1317/20/6/064019
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Published Date

01-06-2010

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Source:

Journal of micromechanics and microengineering, 20 (6) 2010

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

DIMES

Abstract

This paper presents a silicon MEMS capacitive structure to investigate a test methodology for fF-level capacitive sensors’ measurement. The device mimics a capacitive sensor with a changing intermediate layer between the electrodes. A single mask bulk micromachining process is used to fabricate the device, which has a nominal capacitance of 1.2 fF. A high performance measurement setup based on lock-in principle is developed to detect the capacitance variation. The maximum capacitance variation of the fabricated device is 0.31 fF, and the capacitance detection limit is 0.095 aF Hz?1/2.

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