Monostatic Antenna for Wireless Connector

Abstract

To replace the high-speed wired data connector (e.g. USB-C, DisplayPorts, etc.), this thesis proposes an antenna module for a future 60 GHz wireless interface that supports a simultaneous 10 Gb/s up-link and down-link over a short-range channel of 1–10 mm, while remaining invariant to a full 360-degree relative rotation between the two devices. Although the application-level targets are clear, no near-field system model exists that translates them into physical antenna specifications. This work derives that translation and identifies symmetry as the single key antenna parameter, from which high isolation follows before any full-wave simulation is run. A four sequentially rotated circular array of linearly polarized patches with differential feeding is designed, and compared against an existing four-arm Archimedean spiral as baseline.

Both are evaluated on the Co-Channel Interference ratio (CCI), the figure of merit to compare link budget and port isolation for a near-field channel, rather than on far-field measures such as axial ratio. CCI of above 25 dB is required at system level, as low power consumption is targeted by leveraging low-order modulation scheme (e.g. QPSK). Because the 60 GHz laminate process is outside the present scope, the proposed concept is designed and simulated at 11–12 GHz on a multi-layer PCB as a frequency-scaled proof of concept, and the comparison is therefore made on normalized, frequency-independent metrics. The comparison is made at the one separation the two designs share, 1.15𝜆, over a full sweep of the two ways the devices can be misaligned: relative rotation about the link axis, and radial offset between the apertures. With the apertures aligned the spiral baseline reaches 32.4 dB against 24.8 dB for the proposed array; with a radial offset of roughly 0.4𝜆 the spiral falls to 21.5 dB while the proposed array rises to 42.5 dB. What separates the two concepts is therefore their sensitivity to misalignment rather than the absolute margin, and the proposed array is the architecture carried forward.