Towards Robust Implementation of Memristor Crossbar Logic Circuits

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Towards Robust Implementation of Memristor Crossbar Logic Circuits

Conference Paper (2016)

Author(s)

L. Xie (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group

Computer Engineering

Robustness Nanowires Resistance Equivalent circuits Nanowires Memristors Adders Switches Frequency modulation Logic circuits Memristor circuits SPICE simulations VLSI circuits Floating nanowires Full adder Half-select voltages Logic operations Memristor crossbar logic circuits Realization parameter constraints Robust implementation Sneak path currents Word length 1 bit

DOI related publication

https://doi.org/10.1109/PRIME.2016.7519463 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:af096d43-5b6b-4cc5-8786-896d4b3b4eea

More Info

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Publication Year

2016

Language

English

Research Group

Computer Engineering

Pages (from-to)

1-4

ISBN (print)

978-1-5090-0493-5

Event

PRIME 2016 (2016-06-27 - 2016-06-30), Lisbon, Portugal

Downloads counter

158

Abstract

Memristor crossbar is a promising technology for future VLSI circuits due to its scalability, non-volatility, high integration density, etc. However, sneak path currents in the crossbar pose major robustness challenges. One proposed solution is applying half-select voltages to floating nanowires (which are not involved in logic operations). This paper analyzes the sneak path issue after applying half-select voltages, and then uses this analysis to derive a set of realization parameter constraints for robustness. In addition, the constraints are used to estimate maximal crossbar size of logic circuits. As a case study, a one-bit full adder is implemented and verified with SPICE simulations; the results show that the proposed approach accurately predicts the impact of sneak path currents with a maximal error of 0.06V.