PPM reduction on embedded memories in system on chip

Conference paper (2007)
Faculty
Electrical Engineering, Mathematics and Computer Science (EEMCS) (TU Delft)
Copyright: © 2007 Hamdioui, S.; Al-Ars, Z.; Jimenez, J.; Calero, J.
Memory testing Dynamic faults Static faults PPM reduction
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Published Date

2007

Reuse Rights

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Source:

12th IEEE European Test Symposium, ETS '07, Freiburg, Germany, May 20-24, 2007

ISBN:

0-7695-2827-9 ; ISSN 1530-1877

Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests are industrially evaluated together with the traditional tests at "Design of Systems on Silicon (DS2)" in Spain in order to (a) validate the used fault models and (b) investigate the added value of the new tests and their impact on the PPM level. The preliminary silicon results are presented and analyzed. They validate some of the new dynamic fault models and show the importance of considering dynamic faults for high outgoing product quality.

Files

2007-28.pdf
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