DLL Based Single Slope ADC For CMOS Image Sensor Column Readout

Master thesis (2011)

Authors

Contributors

A. Theuwissen (mentor)
A. Munir (mentor)
Programme
Microelectronics (EEMCS) (TU Delft)
Copyright: © 2011 Guo, J.
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Published Date

25-08-2011

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Programme

Microelectronics

Abstract

This thesis presents a Delay Locked Loop(DLL) based Single Slope ADC. Compared to the convertional Single Slope ADC, the readout speed is increased by 16 times. A DLL is designed with a start-controlled Phase Frequency Detector (PFD), a differential ended Charge Pump (CP) and fully differential Delay Cells (DC). The multi-stage comparator with auto-zero technique to minimize the offset is also designed which can guarantee low Fixed Patten Noise (FPN). Some digital circuit designs such as the ripple counter and the cyclic thermometer code to binary code encoder are also included. For the Correlated Double Sampling (CDS), the architecture with two comparators and XOR gate is implemented which also aims to increase the readout speed. This ADC can achieve 12-bit resolution with 3us readout time. The total power consumption for 330 columns is 82mW, with the FoM=0.182 for the column level ADC.