Loop parallelization for reconfigurable architectures

Conference paper (2007)

Authors

OS Dragomir Computer Engineering - EEMCS
E Moscu Panainte Computer Engineering - EEMCS
K.L.M. Bertels Computer Engineering - EEMCS
Research Group
Computer Engineering (EEMCS) (TU Delft)
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Published Date

2007

Language

Undefined/Unknown

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering