A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

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A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

Journal Article (2021)

Author(s)

Chao Chieh Li (University College Dublin, Taiwan Semiconductor Manufacturing Company (TSMC))

Min Shueh Yuan (Taiwan Semiconductor Manufacturing Company (TSMC))

Chia Chun Liao (Taiwan Semiconductor Manufacturing Company (TSMC))

Chih Hsien Chang (Taiwan Semiconductor Manufacturing Company (TSMC))

Yu Tso Lin (Taiwan Semiconductor Manufacturing Company (TSMC))

Tsung Hsien Tsai (Taiwan Semiconductor Manufacturing Company (TSMC))

Tien Chien Huang (Taiwan Semiconductor Manufacturing Company (TSMC))

Hsien Yuan Liao (Taiwan Semiconductor Manufacturing Company (TSMC))

Robert Bogdan Staszewski (TU Delft - Electronics, University College Dublin)

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Research Group

Electronics

Transformer Oscillators Transformer FinFET Metastability Tuning Fractional-N Q-factor Fractional-N Time-to-digital converter (TDC) All-digital phase-locked loop (ADPLL) Couplings Clocks Phase locked loops Inductors Compact area Metastability TDC gain estimator Wide tuning range (TR). Compact area Wide tuning range (TR) Time-to-digital converter (TDC)

DOI related publication

https://doi.org/10.1109/TCSI.2021.3059484 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:c61a1e6a-7760-457f-b79f-638bd2f3baf7

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Publication Year

2021

Language

English

Research Group

Electronics

Issue number

5

Volume number

68

Article number

9382013

Pages (from-to)

1881-1891

Downloads counter

383

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Abstract

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of -247dB, and normalized TR and area (FOMTA) of -262dB.

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