Modeling of strained CMOS on disposable SiGe dots

Abstract

We proposed a new non-planar disposable SiGe dot (d-Dot) MOSFET based on Si-on-nothing technology. The new device concepts’ relies on self-assembled single-crystalline d-Dot. The d-Dot MOSFET is prone to a particularly high strain/stress from the underlaying SiGe 3D islands. We show that more than 50% higher mobilities of electrons can be obtained as indicated by 3D simulations performed throughout the entire fabrication process. Then, fully-depleted SOI MOSFET and d-Dot MOSFET are compared in term of short channel effects, parasitic capacitance effects and self-heating effects.