A FeFET-Based Reconfigurable Computing Platform
J.J. Teunissen (TU Delft - Electrical Engineering, Mathematics and Computer Science)
J.S.S.M. Wong – Mentor (TU Delft - Electrical Engineering, Mathematics and Computer Science)
C. Gao – Graduation committee member (TU Delft - Electrical Engineering, Mathematics and Computer Science)
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Abstract
This thesis delves into reconfigurable computing architecture (RCA) design based on emerging embedded non-volatile memory (eNVM) technologies. Traditional Field-Programmable Gate Arrays, while efficient, face inherent limitations when it comes to power consumption and reconfigurability, primarily due to their set amount of resources and reliance on SRAM cells. Emerging eNVM technologies, such as STT-MTJ, ReRAM, and FeFET, offer potential alternatives, each with unique benefits and drawbacks. In this research, we introduce a novel RCA architecture built upon FeFET eNVM technology, which we called the 'Unified Tile'. This architecture is distinctive for its 2D layout of homogeneous tiles, these tiles integrate the three primary functions of an RCA: memory, interconnect, and logic. Our proposed design emphasizes the potential advantages of eNVM technologies over conventional SRAM-based FPGA components.
To validate our design, we employ an event-based simulator developed on the SystemC framework. Through evaluations and benchmarks, our 'Unified Tile' demonstrated notable improvements in power, area, and delay metrics compared to traditional FPGAs. Moreover, when compared with other state-of-the-art eNVM-based RCAs, our architecture showcased competitive, performance. These findings underscore the potential of eNVM-based RCAs as a viable alternative to SRAM-based FPGAs. This research shows the potential of eNVM technologies in reconfigurable computing architectures, with an emphasis on a FeFET-based design. It has also highlighted areas of concern, especially in programming latency, for these emerging technologies.